During front end-of-the-line processing, a plurality of semiconductor devices (e.g., transistors, resistors, capacitors, and the like) is formed on a semiconductor wafer. During back end-of-the-line (BEOL) processing, the semiconductor devices are interconnected to form a plurality of integrated circuits on the wafer, which are subsequently separated into individual die during wafer dicing. Interconnection of the semiconductor devices is accomplished via the formation of a plurality of BEOL layers, which include successively-deposited metallization and intermetal dielectric layers. Relatively large (e.g., >50 microns) metal pads are typically formed in the BEOL layers during back end-of-the-line processing to permit inline testing of device functionality, switching speed, and various other electrical characteristics of the fully or partially completed circuit (e.g., metallization layer resistance, leakage between closely-spaced lines, etc.). By industry convention, the metal pads formed in the BEOL layers are commonly referred to as “bondpads,” whether or not the pads are actually utilized for bonding. In the case of production wafers, the bondpads are typically disposed within the wafer's saw lanes so as not to detract from the area available for active devices. During inline testing, electrical measurements are performed utilizing an electrical testing apparatus or “prober,” which often includes a probe card carrying multiple cantilevered needles. During each inline testing event, the cantilevered probe needles are placed in contact with the exposed bondpads and electrical measurements are then taken.
To ensure adequate electrical contact during inline testing, probe needles are typically pressed against the bondpads with sufficient force to cause needle deflection. During touch down, the probe needle can scratch or gouge the upper contact surface of the tested bondpad, which may result in the pile-up of bondpad material (e.g., copper) on the bondpad's contact surface. Pile-up of the bondpad material can prevent the subsequently-deposited interlayer dielectric from forming a complete seal over the bondpad, which, in turn, may result in the formation of one or more ingress paths through which water may seep during subsequent processing steps (e.g., wafer wet clean). Residual water can react with and oxidize the metal liner subsequently deposited over the sidewalls of contact openings and trenches, thereby decreasing the effectiveness of the metal liner as a barrier to conductive (e.g., copper) plugs later formed within contact openings. In addition, residual water can upset the etching process (e.g., reactive ion etching) utilized to pattern the interlay dielectric deposited over the scratched bondpad. The ingress of water due to bondpad gouging is thus problematic for test wafers, as it can compromise the semiconductor devices tested in a prior metallization level. The ingress of water is also problematic for production wafers; even when the bondpads are formed in the production wafer's saw lanes, residual water can diffuse significant distances within the interlayer dielectric and potentially reach the active areas of the circuit. Diffusion of residual water is especially problematic for production wafers employing ultra low-k (“ULK”) dielectrics, which often have relatively high porosities that promote the widespread wicking of residual water through the ULK dielectric.
Considering the above, it would be desirable to provide embodiments of a method for fabricating an integrated circuit wherein the likelihood of bondpad gouging, and thus the likelihood of residual water ingress, is significantly reduced or eliminated. Ideally, embodiments of such integrated circuit fabrication method would be compatible with ULK dielectrics and would minimize production costs by utilizing fabrication techniques already incorporated within mainstream circuit production or likely to be incorporated into mainstream circuit production in the near future. It would also be desirable to provide embodiments of an integrated circuit that can be produced utilizing such a circuit fabrication method and that includes unique structural means for avoiding frontside bondpad gouging. Other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended Claims, taken in conjunction with the accompanying Drawings and the foregoing Technical Field and Background.